1. Field of the Invention
The present invention relates generally to a solid state memory system for a data storage and retrieval having a memory controller for controlling access to a non-volatile memory of the solid state memory system and particularly to a method and apparatus for accessing data stored within the non-volatile memory of the solid state memory system at an increased speed when the data has a repetitive pattern.
2. Description of the Prior Art
It is known to use solid state memory systems to try to emulate magnetic disk storage devices in computer systems. In particular, it is an aim of the industry to try to increase the speed of operation of solid state memory systems to better emulate magnetic disc storage.
A typical memory system comprises a non-volatile memory, such as a Flash memory, and a controller. The flash memory has individually addressable sectors wherein a memory sector is a group of flash memory locations which is allocated for storage of one Logical Sector. a memory sector need not be a physical partition within Flash memory, nor need it be contiguous Flash memory locations, so the memory sector address may be a virtual address conveniently used by the controller. The controller writes data structures to and reads data structures from the memory, and translates logical addresses received from the host to physical, or virtual addresses, of the memory sectors in the memory.
When a logical sector write command is received from the host, the controller translates a logical address received from the host and allocates a memory sector for the logical sector to be written to. The controller is also responsible for maintaining a table of logical addresses with respective physical addresses which have been allocated by the controller. The table is referred to as the Sector Allocation Table or SAT. there is also, in some cases, a system or hierarchy of SATs to provide improved ease of access and to reduce the update frequency required.
The physical or virtual, sector addresses in the SAT are typically ordered by logical sector address, where the Nth SAT entry includes the physical address of a sector to which data having logical address N has been written. When a sector read command is received from the host, the controller looks up a logical sector address received from the host in the SAT in order to obtain the physical sector address which the controller previously allocated to the logical sector. On some occasions one SAT entry is used to define the address of a group of contiguous memory sectors containing a group of contiguous logical sectors.
A feature of the flash memory is that the flash memory must be pre-erased before the data can be written. This means that, in general, in the flash memory system, when a logical sector is written, the obsolete copy of the logical sector should be erased before or after. Here, the term erased memory sector will be used for a memory sector which has all the cells erased. Quite often the memory sectors are not individually erasable, but, grouped to be erasable in units or blocks. The controller can use various methods to maintain the flash memory. Any memory sector which has been written to will be treated by the controller as a memory sector which has not been erased.
The host can issue a sector erase command to erase the logical sector in the memory in order to delete all the sector data and pre-erase the card for a faster sector write operation in the future. This results in the sector write operation consisting of Flash memory writes only and no erases. The term erased logical sector is generally used not only for a logical sector which has been erased, but, also for a sector which has not yet been written. Due to the complexity of flash memory organization and complexity of its maintenance, various algorithms can be used which allows an erased logical sector to be temporarily marked in the SAT as obsolete, but, the memory sector containing the logical sector can be erased later. The example of such a memory system is illustrated in the “Memory System” detailed in patent application WO 00/49488 PCT/GB00,00550). FIG. 1 (prior art) illustrates the address translation algorithm of the Memory System of WO 00/49488. FIG. 2 illustrates the sector read operation of the Memory System of WO 00/49488. WO 00/49488 describes the technique of using the SAT Table not only to define physical locations of the written logical sectors, but, also to mark them as deleted or bad. In the case of the deleted or never written sector the corresponding SAT entry includes the virtual address value showing that the sector includes no data the controller sets all the bytes of the sector data buffer to all 1s and the sector then will be output to the host.
Thus, a need arises to obviate or mitigate at least one of the aforementioned problems.